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144 lines
5.3 KiB
C
144 lines
5.3 KiB
C
/**
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******************************************************************************
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* @file stm32h5xx_ll_icache.c
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* @author MCD Application Team
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* @brief ICACHE LL module driver.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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#if defined(USE_FULL_LL_DRIVER)
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h5xx_ll_icache.h"
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#ifdef USE_FULL_ASSERT
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#include "stm32_assert.h"
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#else
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#define assert_param(expr) ((void)0U)
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#endif /* USE_FULL_ASSERT */
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/** @addtogroup STM32H5xx_LL_Driver
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* @{
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*/
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#if defined(ICACHE)
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/** @defgroup ICACHE_LL ICACHE
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/** @defgroup ICACHE_LL_Private_Macros ICACHE Private Macros
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* @{
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*/
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#if defined(ICACHE_CRRx_REN)
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#define IS_LL_ICACHE_REGION(__VALUE__) (((__VALUE__) == LL_ICACHE_REGION_0) || \
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((__VALUE__) == LL_ICACHE_REGION_1) || \
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((__VALUE__) == LL_ICACHE_REGION_2) || \
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((__VALUE__) == LL_ICACHE_REGION_3))
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#define IS_LL_ICACHE_REGION_SIZE(__VALUE__) (((__VALUE__) == LL_ICACHE_REGIONSIZE_2MB) || \
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((__VALUE__) == LL_ICACHE_REGIONSIZE_4MB) || \
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((__VALUE__) == LL_ICACHE_REGIONSIZE_8MB) || \
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((__VALUE__) == LL_ICACHE_REGIONSIZE_16MB) || \
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((__VALUE__) == LL_ICACHE_REGIONSIZE_32MB) || \
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((__VALUE__) == LL_ICACHE_REGIONSIZE_64MB) || \
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((__VALUE__) == LL_ICACHE_REGIONSIZE_128MB))
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#define IS_LL_ICACHE_MASTER_PORT(__VALUE__) (((__VALUE__) == LL_ICACHE_MASTER1_PORT) || \
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((__VALUE__) == LL_ICACHE_MASTER2_PORT))
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#define IS_LL_ICACHE_OUTPUT_BURST(__VALUE__) (((__VALUE__) == LL_ICACHE_OUTPUT_BURST_WRAP) || \
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((__VALUE__) == LL_ICACHE_OUTPUT_BURST_INCR))
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#endif /* ICACHE_CRRx_REN */
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/**
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* @}
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*/
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/* Private function prototypes -----------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup ICACHE_LL_Exported_Functions
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* @{
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*/
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#if defined(ICACHE_CRRx_REN)
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/** @addtogroup ICACHE_LL_EF_REGION_Init
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* @{
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*/
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/**
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* @brief Configure and enable the memory remapped region.
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* @note The Instruction Cache and corresponding region must be disabled.
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* @param Region This parameter can be one of the following values:
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* @arg @ref LL_ICACHE_REGION_0
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* @arg @ref LL_ICACHE_REGION_1
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* @arg @ref LL_ICACHE_REGION_2
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* @arg @ref LL_ICACHE_REGION_3
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* @param pICACHE_RegionStruct pointer to a @ref LL_ICACHE_RegionTypeDef structure.
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* @retval None
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*/
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void LL_ICACHE_ConfigRegion(uint32_t Region, const LL_ICACHE_RegionTypeDef *const pICACHE_RegionStruct)
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{
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__IO uint32_t *p_reg;
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uint32_t value;
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/* Check the parameters */
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assert_param(IS_LL_ICACHE_REGION(Region));
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assert_param(IS_LL_ICACHE_REGION_SIZE(pICACHE_RegionStruct->Size));
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assert_param(IS_LL_ICACHE_MASTER_PORT(pICACHE_RegionStruct->TrafficRoute));
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assert_param(IS_LL_ICACHE_OUTPUT_BURST(pICACHE_RegionStruct->OutputBurstType));
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/* Get region control register address */
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p_reg = &(ICACHE->CRR0) + (1U * Region);
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/* Region 2MB: BaseAddress size 8 bits, RemapAddress size 11 bits */
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/* Region 4MB: BaseAddress size 7 bits, RemapAddress size 10 bits */
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/* Region 8MB: BaseAddress size 6 bits, RemapAddress size 9 bits */
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/* Region 16MB: BaseAddress size 5 bits, RemapAddress size 8 bits */
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/* Region 32MB: BaseAddress size 4 bits, RemapAddress size 7 bits */
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/* Region 64MB: BaseAddress size 3 bits, RemapAddress size 6 bits */
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/* Region 128MB: BaseAddress size 2 bits, RemapAddress size 5 bits */
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value = ((pICACHE_RegionStruct->BaseAddress & 0x1FFFFFFFU) >> 21U) & \
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(0xFFU & ~(pICACHE_RegionStruct->Size - 1U));
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value |= ((pICACHE_RegionStruct->RemapAddress >> 5U) & \
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((uint32_t)(0x7FFU & ~(pICACHE_RegionStruct->Size - 1U)) << ICACHE_CRRx_REMAPADDR_Pos));
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value |= (pICACHE_RegionStruct->Size << ICACHE_CRRx_RSIZE_Pos) | pICACHE_RegionStruct->TrafficRoute | \
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pICACHE_RegionStruct->OutputBurstType;
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*p_reg = (value | ICACHE_CRRx_REN); /* Configure and enable region */
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}
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/**
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* @}
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*/
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#endif /* ICACHE_CRRx_REN */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* ICACHE */
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/**
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* @}
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*/
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#endif /* USE_FULL_LL_DRIVER */
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