diff --git a/.mxproject b/.mxproject index 4bd0b2f..8d1e4ab 100644 --- a/.mxproject +++ b/.mxproject @@ -1,8 +1,8 @@ [PreviousLibFiles] -LibFiles=Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_gpio.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_system.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_exti.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_cortex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_bus.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_rcc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_crs.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_utils.h;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_utils.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_exti.c;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_pwr.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dma.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dmamux.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_icache.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_tim.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_usart.h;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_gpio.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_exti.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_rcc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_icache.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_pwr.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_tim.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_dma.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_usart.c;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_gpio.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_system.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_exti.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_cortex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_bus.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_rcc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_crs.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_utils.h;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_utils.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_exti.c;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_pwr.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dma.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dmamux.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_icache.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_tim.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_usart.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h533xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Source\Templates\system_stm32h5xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; +LibFiles=Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_gpio.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_system.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_exti.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_cortex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_bus.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_rcc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_crs.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_utils.h;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_utils.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_exti.c;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_pwr.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dma.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dmamux.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_icache.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_tim.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_usart.h;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_gpio.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_exti.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_rcc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_dma.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_icache.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_pwr.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_tim.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_usart.c;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_gpio.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_system.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_exti.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_cortex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_bus.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_rcc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_crs.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_utils.h;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_utils.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_exti.c;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_pwr.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dma.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dmamux.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_icache.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_tim.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_usart.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h533xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Source\Templates\system_stm32h5xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; [PreviousUsedCubeIDEFiles] -SourceFiles=Core\Src\main.c;Core\Src\stm32h5xx_it.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_utils.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_exti.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_gpio.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_rcc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_icache.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_pwr.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_tim.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_dma.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_usart.c;Drivers\CMSIS\Device\ST\STM32H5xx\Source\Templates\system_stm32h5xx.c;Core\Src\system_stm32h5xx.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_utils.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_exti.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_gpio.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_rcc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_icache.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_pwr.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_tim.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_dma.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_usart.c;Drivers\CMSIS\Device\ST\STM32H5xx\Source\Templates\system_stm32h5xx.c;Core\Src\system_stm32h5xx.c;;; +SourceFiles=Core\Src\main.c;Core\Src\stm32h5xx_it.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_utils.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_exti.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_gpio.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_rcc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_dma.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_icache.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_pwr.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_tim.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_usart.c;Drivers\CMSIS\Device\ST\STM32H5xx\Source\Templates\system_stm32h5xx.c;Core\Src\system_stm32h5xx.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_utils.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_exti.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_gpio.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_rcc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_dma.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_icache.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_pwr.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_tim.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_usart.c;Drivers\CMSIS\Device\ST\STM32H5xx\Source\Templates\system_stm32h5xx.c;Core\Src\system_stm32h5xx.c;;; HeaderPath=Drivers\STM32H5xx_HAL_Driver\Inc;Drivers\CMSIS\Device\ST\STM32H5xx\Include;Drivers\CMSIS\Include;Core\Inc; CDefines=USE_FULL_LL_DRIVER;HSE_VALUE:16000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;EXTERNAL_CLOCK_VALUE:12288000;HSI_VALUE:64000000;LSI_VALUE:32000;VDD_VALUE:3300;STM32H533xx;USE_FULL_LL_DRIVER;HSE_VALUE:16000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;EXTERNAL_CLOCK_VALUE:12288000;HSI_VALUE:64000000;LSI_VALUE:32000;VDD_VALUE:3300; diff --git a/Core/Inc/main.h b/Core/Inc/main.h index b0a7f2e..a6f0bc3 100644 --- a/Core/Inc/main.h +++ b/Core/Inc/main.h @@ -27,6 +27,7 @@ extern "C" { #endif /* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_ll_dma.h" #include "stm32h5xx_ll_icache.h" #include "stm32h5xx_ll_pwr.h" #include "stm32h5xx_ll_crs.h" @@ -36,7 +37,6 @@ extern "C" { #include "stm32h5xx_ll_exti.h" #include "stm32h5xx_ll_cortex.h" #include "stm32h5xx_ll_utils.h" -#include "stm32h5xx_ll_dma.h" #include "stm32h5xx_ll_tim.h" #include "stm32h5xx_ll_usart.h" #include "stm32h5xx_ll_gpio.h" diff --git a/Core/Inc/usart3_dma.h b/Core/Inc/usart3_dma.h new file mode 100644 index 0000000..b07b4d3 --- /dev/null +++ b/Core/Inc/usart3_dma.h @@ -0,0 +1,18 @@ +#ifndef __USART3_IT_H__ +#define __USART3_IT_H__ + +#include +#include "usart3_dma_cfg.h" + + +extern uint8_t Usart3RxDmaBuf[USART3_RXDMA_BUF_SIZE]; + +extern void Usart3_DMA_Init(void (*)(const uint8_t* data, uint16_t len)); +extern void Usart3_DMA_Task(); +extern void Usart3_PutByte(uint8_t d); +extern void Usart3_PutData(const void* src, uint16_t n); +extern int16_t Usart3_GetByte(void); + + +#endif + diff --git a/Core/Inc/usart3_dma_cfg.h b/Core/Inc/usart3_dma_cfg.h new file mode 100644 index 0000000..b89be2f --- /dev/null +++ b/Core/Inc/usart3_dma_cfg.h @@ -0,0 +1,15 @@ +#ifndef __USART3_IT_CFG_H__ +#define __USART3_IT_CFG_H__ + +#include "stm32h5xx_ll_dma.h" + + +#define USART3_RXDMA_BUF_SIZE 2048 +#define USART3_TXDMA_BUF_SIZE 2048 + +#define USART3_GPDMA GPDMA1 +#define USART3_DMA_TX_CHANNEL LL_DMA_CHANNEL_0 +#define USART3_DMA_RX_CHANNEL LL_DMA_CHANNEL_1 + + +#endif // __USART3_CFG_H__ diff --git a/Core/Src/main.c b/Core/Src/main.c index b476c65..ecfcf04 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -21,10 +21,12 @@ /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ +#include #include #include "disp7seg.h" #include "printf.h" +#include "usart3_dma.h" #include "uart5_it.h" /* USER CODE END Includes */ @@ -36,6 +38,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN PD */ +#define ARRAY_COUNT(arr) (sizeof(arr) / sizeof((arr)[0])) /* USER CODE END PD */ @@ -46,21 +49,27 @@ /* Private variables ---------------------------------------------------------*/ +LL_DMA_LinkNodeTypeDef Node_GPDMA1_Channel1; + /* USER CODE BEGIN PV */ + /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); void PeriphCommonClock_Config(void); static void MX_GPIO_Init(void); +static void MX_GPDMA1_Init(void); static void MX_ICACHE_Init(void); static void MX_TIM5_Init(void); static void MX_TIM2_Init(void); -static void MX_UART5_Init(void); static void MX_USART3_UART_Init(void); +static void MX_UART5_Init(void); /* USER CODE BEGIN PFP */ +uint8_t Usart3_TxBufWrite(const void* src, size_t n, uint8_t start); + /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ @@ -93,6 +102,12 @@ void uart_putc (void* p, char c) { +void ProcessUsart3RxData(const uint8_t* data, uint16_t len) { + for (uint16_t i = 0; i < len; i++) { + printf("%c", data[i]); + } +} + /* USER CODE END 0 */ /** @@ -132,12 +147,15 @@ int main(void) /* Initialize all configured peripherals */ MX_GPIO_Init(); + MX_GPDMA1_Init(); MX_ICACHE_Init(); MX_TIM5_Init(); MX_TIM2_Init(); - MX_UART5_Init(); MX_USART3_UART_Init(); + MX_UART5_Init(); /* USER CODE BEGIN 2 */ + init_printf(NULL, &uart_putc); + LL_TIM_GenerateEvent_UPDATE(TIM2); LL_TIM_EnableCounter(TIM2); LL_TIM_GenerateEvent_UPDATE(TIM5); @@ -151,6 +169,7 @@ int main(void) DispPutDigit(3, ' ', 0); ShiftReg_Update(); + Usart3_DMA_Init(ProcessUsart3RxData); Uart5_Init(); printf("Hello printf\n"); @@ -171,12 +190,9 @@ int main(void) static uint8_t cnt = 0; DispPutDigit(2, 'A'+cnt, 0); cnt = (cnt + 1) % 16; - static uint32_t Trefus = 0; - uint32_t t = usTimerGetAbs(); - uint32_t tdif = t - Trefus; - printf("%6luus\n", tdif); - Trefus = t; - LL_USART_TransmitData8(USART3, 'A' + cnt); // direct send without buffer and interrupt + char s[256]; + sprintf(s, "%u: Hello DMA World! This is a long message to test the double buffering mechanism of USART3 Tx DMA.\n", cnt); + Usart3_TxBufWrite(s, strlen(s), cnt&0x04); // write data and request flush } static uint32_t Tick100msRef = 0; @@ -186,16 +202,15 @@ int main(void) DispPutDigit(3, ' ', dot); } - if (LL_USART_IsActiveFlag_RXNE_RXFNE(USART3)) { // check if data received - char rxch = LL_USART_ReceiveData8(USART3); // direct receive without buffer and interrupt - DispPutDigit(1, rxch, 1); - } - int16_t ch = Uart5_GetByte(); if (ch != -1) { // if data received char c = ch; DispPutDigit(0, c, 0); } + + Usart3_DMA_Task(); // handle USART3 DMA rx/tx + + /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ @@ -282,6 +297,34 @@ void PeriphCommonClock_Config(void) } +/** + * @brief GPDMA1 Initialization Function + * @param None + * @retval None + */ +static void MX_GPDMA1_Init(void) +{ + + /* USER CODE BEGIN GPDMA1_Init 0 */ + + /* USER CODE END GPDMA1_Init 0 */ + + /* Peripheral clock enable */ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPDMA1); + + /* GPDMA1 interrupt Init */ + NVIC_SetPriority(GPDMA1_Channel0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + NVIC_SetPriority(GPDMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + + /* USER CODE BEGIN GPDMA1_Init 1 */ + + /* USER CODE END GPDMA1_Init 1 */ + /* USER CODE BEGIN GPDMA1_Init 2 */ + + /* USER CODE END GPDMA1_Init 2 */ + +} + /** * @brief ICACHE Initialization Function * @param None @@ -453,11 +496,22 @@ static void MX_USART3_UART_Init(void) /* USER CODE BEGIN USART3_Init 0 */ + // WARNING + // Remove the second redefinition of NodeConfig after Cube MX code generation. + LL_DMA_InitNodeTypeDef NodeConfig = {0}; + + NodeConfig.SrcAddress = (uint32_t)LL_USART_DMA_GetRegAddr(USART3, LL_USART_DMA_REG_DATA_RECEIVE); + NodeConfig.DestAddress = (uint32_t)&Usart3RxDmaBuf; + NodeConfig.BlkDataLength = ARRAY_COUNT(Usart3RxDmaBuf); + + /* USER CODE END USART3_Init 0 */ LL_USART_InitTypeDef USART_InitStruct = {0}; LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + LL_DMA_InitLinkedListTypeDef DMA_InitLinkedListStruct = {0}; + LL_DMA_InitTypeDef DMA_InitStruct = {0}; LL_RCC_SetUSARTClockSource(LL_RCC_USART3_CLKSOURCE_PCLK1); @@ -478,8 +532,83 @@ static void MX_USART3_UART_Init(void) GPIO_InitStruct.Alternate = LL_GPIO_AF_7; LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + /* USART3 DMA Init */ + + /* GPDMA1_REQUEST_USART3_RX Init */ + NodeConfig.DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT1; + NodeConfig.DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE; + NodeConfig.DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE; + NodeConfig.DestBurstLength = 1; + NodeConfig.DestIncMode = LL_DMA_DEST_INCREMENT; + NodeConfig.DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE; + NodeConfig.SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0; + NodeConfig.SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE; + NodeConfig.DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD; + NodeConfig.SrcBurstLength = 1; + NodeConfig.SrcIncMode = LL_DMA_SRC_FIXED; + NodeConfig.SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE; + NodeConfig.TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER; + NodeConfig.Mode = LL_DMA_NORMAL; + NodeConfig.TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED; + NodeConfig.BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST; + NodeConfig.Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; + NodeConfig.Request = LL_GPDMA1_REQUEST_USART3_RX; + NodeConfig.UpdateRegisters = (LL_DMA_UPDATE_CTR1 | LL_DMA_UPDATE_CTR2 | LL_DMA_UPDATE_CBR1 | LL_DMA_UPDATE_CSAR | LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CTR3 | LL_DMA_UPDATE_CBR2 | LL_DMA_UPDATE_CLLR); + NodeConfig.NodeType = LL_DMA_GPDMA_LINEAR_NODE; + LL_DMA_CreateLinkNode(&NodeConfig, &Node_GPDMA1_Channel1); + + LL_DMA_ConnectLinkNode(&Node_GPDMA1_Channel1, LL_DMA_CLLR_OFFSET5, &Node_GPDMA1_Channel1, LL_DMA_CLLR_OFFSET5); + + /* Next function call is commented because it will not compile as is. The Node structure address has to be cast to an unsigned int (uint32_t)pNode_DMAxCHy */ + /* + + */ + LL_DMA_SetLinkedListBaseAddr(GPDMA1, LL_DMA_CHANNEL_1, (uint32_t)&Node_GPDMA1_Channel1); + + DMA_InitLinkedListStruct.Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT; + DMA_InitLinkedListStruct.LinkStepMode = LL_DMA_LSM_FULL_EXECUTION; + DMA_InitLinkedListStruct.LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT1; + DMA_InitLinkedListStruct.TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER; + LL_DMA_List_Init(GPDMA1, LL_DMA_CHANNEL_1, &DMA_InitLinkedListStruct); + + /* GPDMA1_REQUEST_USART3_TX Init */ + DMA_InitStruct.SrcAddress = 0x00000000U; + DMA_InitStruct.DestAddress = 0x00000000U; + DMA_InitStruct.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH; + DMA_InitStruct.BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST; + DMA_InitStruct.DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD; + DMA_InitStruct.SrcBurstLength = 1; + DMA_InitStruct.DestBurstLength = 1; + DMA_InitStruct.SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE; + DMA_InitStruct.DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE; + DMA_InitStruct.SrcIncMode = LL_DMA_SRC_INCREMENT; + DMA_InitStruct.DestIncMode = LL_DMA_DEST_FIXED; + DMA_InitStruct.Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT; + DMA_InitStruct.BlkDataLength = 0x00000000U; + DMA_InitStruct.TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER; + DMA_InitStruct.TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED; + DMA_InitStruct.TriggerSelection = 0x00000000U; + DMA_InitStruct.Request = LL_GPDMA1_REQUEST_USART3_TX; + DMA_InitStruct.TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER; + DMA_InitStruct.Mode = LL_DMA_NORMAL; + DMA_InitStruct.SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT1; + DMA_InitStruct.DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0; + DMA_InitStruct.LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT1; + DMA_InitStruct.LinkStepMode = LL_DMA_LSM_FULL_EXECUTION; + DMA_InitStruct.LinkedListBaseAddr = 0x00000000U; + DMA_InitStruct.LinkedListAddrOffset = 0x00000000U; + LL_DMA_Init(GPDMA1, LL_DMA_CHANNEL_0, &DMA_InitStruct); + /* USER CODE BEGIN USART3_Init 1 */ + LL_DMA_ConfigLinkUpdate(GPDMA1, LL_DMA_CHANNEL_1, LL_DMA_UPDATE_CTR1 | LL_DMA_UPDATE_CTR2 |LL_DMA_UPDATE_CBR1 | LL_DMA_UPDATE_CSAR | LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CLLR, (uint32_t)&Node_GPDMA1_Channel1); + LL_DMA_EnableChannel(GPDMA1, LL_DMA_CHANNEL_1); + LL_DMA_SetLinkedListAddrOffset(GPDMA1, LL_DMA_CHANNEL_1, LL_DMA_CLLR_OFFSET5); + LL_USART_EnableDMAReq_RX(USART3); + + LL_DMA_SetDestAddress(GPDMA1, LL_DMA_CHANNEL_0, LL_USART_DMA_GetRegAddr(USART3, LL_USART_DMA_REG_DATA_TRANSMIT)); + LL_USART_EnableDMAReq_TX(USART3); + /* USER CODE END USART3_Init 1 */ USART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1; USART_InitStruct.BaudRate = 115200; @@ -501,6 +630,7 @@ static void MX_USART3_UART_Init(void) LL_USART_Enable(USART3); /* USER CODE BEGIN USART3_Init 2 */ + /* USER CODE END USART3_Init 2 */ } diff --git a/Core/Src/usart3_dma.c b/Core/Src/usart3_dma.c new file mode 100644 index 0000000..b7c92da --- /dev/null +++ b/Core/Src/usart3_dma.c @@ -0,0 +1,238 @@ +/***************************************************************************//** +* @file usart3_dma.c +* @brief UART with DMA +*//****************************************************************************/ + +//------------------------------C library--------------------------------------- +#include +#include +#include +//----------------------------user includes------------------------------------- +#include "usart3_dma.h" +//------------------------------------------------------------------------------ + + + + +/* Private typedefs ----------------------------------------------------------*/ + +typedef struct { + uint8_t BufA[USART3_TXDMA_BUF_SIZE]; + uint8_t BufB[USART3_TXDMA_BUF_SIZE]; + int DataCntA; // data count in BufA + int DataCntB; // data count in BufB + int BufSelTx; // -1:none, 0:A, 1:B + int BufSelWr; // 0:A, 1:B + uint8_t FlushA; + uint8_t FlushB; +} Usart3TxBuf_t; + +typedef void (*FuncProcData)(const uint8_t* data, uint16_t len); + + + +/* Private macros ------------------------------------------------------------*/ + +#define ARRAY_COUNT(arr) (sizeof(arr) / sizeof((arr)[0])) + + +/* Private variables ---------------------------------------------------------*/ +uint8_t Usart3RxDmaBuf[USART3_RXDMA_BUF_SIZE] = {0}; +Usart3TxBuf_t Usart3TxDmaBuf = { {0},{0}, 0, 0, -1, 0 }; + +static FuncProcData ProcRxData = NULL; // function to process received data, set by Usart3_DMA_Init + + +/* Public variables ----------------------------------------------------------*/ + + +/* Functions -----------------------------------------------------------------*/ + + +/***************************************************************************//** +* @brief USART3 init +*//****************************************************************************/ +void Usart3_DMA_Init(void (*procRxData)(const uint8_t* data, uint16_t len)) { + ProcRxData = procRxData; + // USART and DMA initialization code should be generated by Cube MX +} + +/***************************************************************************//** +* @brief USART3 Rx/Tx DMA task, to be called periodically in main loop +*//****************************************************************************/ +void Usart3_DMA_Task() { + // Handle received data from USART3 DMA + static uint32_t LastNDTR = USART3_RXDMA_BUF_SIZE; + static uint32_t WritePos = 0U; + uint32_t curNDTR = LL_DMA_GetBlkDataLength(USART3_GPDMA, USART3_DMA_RX_CHANNEL); + uint32_t newBytes; + if (curNDTR <= LastNDTR) { // no Wrap-Around + newBytes = LastNDTR - curNDTR; + }else { // NDTR is bigger than before: Wrap-Around occurred + newBytes = LastNDTR + (USART3_RXDMA_BUF_SIZE - curNDTR); + } + if (newBytes > 0U) { + uint32_t startPos = WritePos; // start of new data + uint32_t endPos = (WritePos + newBytes) % USART3_RXDMA_BUF_SIZE; // end of new data + if (startPos < endPos) { // no Wrap-Around + ProcRxData(&Usart3RxDmaBuf[startPos], newBytes); + } else { // first: to buffer end, second: from buffer begin + uint32_t part1 = USART3_RXDMA_BUF_SIZE - startPos; + ProcRxData(&Usart3RxDmaBuf[startPos], part1); + + uint32_t part2 = newBytes - part1; + ProcRxData(&Usart3RxDmaBuf[0], part2); + } + // Store new Write Position and NDTR + WritePos = endPos; // next start position for write + LastNDTR = curNDTR; // NTDR value for next cycle + } + + // Handle USART3 Tx DMA transfer complete + if (LL_DMA_IsActiveFlag_TC(USART3_GPDMA, USART3_DMA_TX_CHANNEL)) { + LL_DMA_ClearFlag_TC(USART3_GPDMA, USART3_DMA_TX_CHANNEL); + Usart3TxBuf_t* d = &Usart3TxDmaBuf; + switch (d->BufSelTx) { + case 0: { // transfer from BufA completed + d->BufSelTx = -1; // no transfer ongoing + d->DataCntA = 0; // reset BufA data count + if (d->FlushB) { // flush requested for BufB + // start transfer from BufB + LL_DMA_ClearFlag_TC(USART3_GPDMA, USART3_DMA_TX_CHANNEL); + LL_DMA_SetSrcAddress(USART3_GPDMA, USART3_DMA_TX_CHANNEL, (uint32_t)d->BufB); + LL_DMA_SetBlkDataLength(USART3_GPDMA, USART3_DMA_TX_CHANNEL, d->DataCntB); + LL_DMA_EnableChannel(USART3_GPDMA, USART3_DMA_TX_CHANNEL); + d->BufSelTx = 1; // mark transfer from BufB ongoing + d->BufSelWr = 0; // switch write to BufA + d->FlushB = 0; // clear flush request + } + }break; + case 1: { // transfer from BufB completed + d->BufSelTx = -1; // no transfer ongoing + d->DataCntB = 0; // reset BufB data count + if (d->FlushA) { // flush requested for BufA + // start transfer from BufA + LL_DMA_ClearFlag_TC(USART3_GPDMA, USART3_DMA_TX_CHANNEL); + LL_DMA_SetSrcAddress(USART3_GPDMA, USART3_DMA_TX_CHANNEL, (uint32_t)d->BufA); + LL_DMA_SetBlkDataLength(USART3_GPDMA, USART3_DMA_TX_CHANNEL, d->DataCntA); + LL_DMA_EnableChannel(USART3_GPDMA, USART3_DMA_TX_CHANNEL); + d->BufSelTx = 0; // mark transfer from BufA ongoing + d->BufSelWr = 1; // switch write to BufB + d->FlushA = 0; // clear flush request + } + }break; + } + } +} + +/***************************************************************************//** +* @brief Write data to USART3 Tx buffer, and optionally start DMA transfer if flush is requested +* @param src: data to write +* @param n: count of data +* @param flush: if non-zero, request to start DMA transfer after writing data +*//****************************************************************************/ +uint8_t Usart3_TxBufWrite(const void* src, size_t n, uint8_t flush) { + Usart3TxBuf_t* d = &Usart3TxDmaBuf; + switch (d->BufSelWr) { + case 0: { // BufA selected for write + int newpos = d->DataCntA + n; + if (newpos <= 2 * USART3_TXDMA_BUF_SIZE) { // enough space in the entire buffer + if (d->BufSelTx == 1 && newpos > USART3_TXDMA_BUF_SIZE) { + // transfer from BufB ongoing and BufA overflow + return 4; // overflow: skip data + } + memcpy(&d->BufA[d->DataCntA], src, n); + if (newpos > USART3_TXDMA_BUF_SIZE) { // BufA full + d->DataCntA = USART3_TXDMA_BUF_SIZE; // BufA full + // start transfer from BufA + LL_DMA_ClearFlag_TC(USART3_GPDMA, USART3_DMA_TX_CHANNEL); + LL_DMA_SetSrcAddress(USART3_GPDMA, USART3_DMA_TX_CHANNEL, (uint32_t)d->BufA); + LL_DMA_SetBlkDataLength(USART3_GPDMA, USART3_DMA_TX_CHANNEL, d->DataCntA); + LL_DMA_EnableChannel(USART3_GPDMA, USART3_DMA_TX_CHANNEL); + d->BufSelTx = 0; // mark transfer from BufA ongoing + d->BufSelWr = 1; // switch write to BufB + d->DataCntB = newpos - USART3_TXDMA_BUF_SIZE; // adjust BufB write position + if (flush) { + // BufA flush already started + d->FlushB = 1; // mark BufB flush requested + } + }else { // BufA not full yet + d->DataCntA = newpos; + if (flush) { + if (d->BufSelTx == -1) { // flush requested and no transfer ongoing + // start transfer from BufA + LL_DMA_ClearFlag_TC(USART3_GPDMA, USART3_DMA_TX_CHANNEL); + LL_DMA_SetSrcAddress(USART3_GPDMA, USART3_DMA_TX_CHANNEL, (uint32_t)d->BufA); + LL_DMA_SetBlkDataLength(USART3_GPDMA, USART3_DMA_TX_CHANNEL, d->DataCntA); + LL_DMA_EnableChannel(USART3_GPDMA, USART3_DMA_TX_CHANNEL); + d->BufSelTx = 0; // mark transfer from BufA ongoing + d->BufSelWr = 1; // switch write to BufB + }else { + d->FlushA = 1; // mark BufA flush requested + } + } + } + }else { // not enough space in the entire buffer + return 1; // overflow: skip data + } + }break; + case 1: { // BufB selected for write + int newpos = d->DataCntB + n; + if (newpos <= USART3_TXDMA_BUF_SIZE) { // enough space in BufB + memcpy(&d->BufB[d->DataCntB], src, n); + d->DataCntB = newpos; + if (flush) { + if (d->BufSelTx == -1) { // flush requested and no transfer ongoing + // start transfer from BufB + LL_DMA_ClearFlag_TC(USART3_GPDMA, USART3_DMA_TX_CHANNEL); + LL_DMA_SetSrcAddress(USART3_GPDMA, USART3_DMA_TX_CHANNEL, (uint32_t)d->BufB); + LL_DMA_SetBlkDataLength(USART3_GPDMA, USART3_DMA_TX_CHANNEL, d->DataCntB); + LL_DMA_EnableChannel(USART3_GPDMA, USART3_DMA_TX_CHANNEL); + d->BufSelTx = 1; // mark transfer from BufB ongoing + d->BufSelWr = 0; // switch write to BufA + }else { + d->FlushB = 1; // mark BufB flush requested + } + } + }else { // not enough space in BufB + // try to flush BufB if possible + if (d->BufSelTx == -1) { // no transfer ongoing + // start transfer from BufB + LL_DMA_ClearFlag_TC(USART3_GPDMA, USART3_DMA_TX_CHANNEL); + LL_DMA_SetSrcAddress(USART3_GPDMA, USART3_DMA_TX_CHANNEL, (uint32_t)d->BufB); + LL_DMA_SetBlkDataLength(USART3_GPDMA, USART3_DMA_TX_CHANNEL, d->DataCntB); + LL_DMA_EnableChannel(USART3_GPDMA, USART3_DMA_TX_CHANNEL); + d->BufSelTx = 1; // mark transfer from BufB ongoing + d->BufSelWr = 0; // switch write to BufA + } + if (d->BufSelTx != 0) { // BufA ready to write (not being transmitted) + d->BufSelWr = 0; // switch write to BufA + if (n <= USART3_TXDMA_BUF_SIZE) { // enough space in BufA + memcpy(d->BufA, src, n); + d->DataCntA = n; + if (flush) { // flush requested + if (d->BufSelTx == -1) { // no transfer ongoing + // start transfer from BufA + LL_DMA_ClearFlag_TC(USART3_GPDMA, USART3_DMA_TX_CHANNEL); + LL_DMA_SetSrcAddress(USART3_GPDMA, USART3_DMA_TX_CHANNEL, (uint32_t)d->BufA); + LL_DMA_SetBlkDataLength(USART3_GPDMA, USART3_DMA_TX_CHANNEL, d->DataCntA); + LL_DMA_EnableChannel(USART3_GPDMA, USART3_DMA_TX_CHANNEL); + d->BufSelTx = 0; // mark transfer from BufA ongoing + d->BufSelWr = 1; // switch write to BufB + }else { // transfer ongoing + d->FlushA = 1; // mark BufA flush requested + } + } + }else { + return 2; // overflow: skip data + } + }else { + return 3; // overflow: skip data + } + } + }break; + } + return 0; // no error +} + + diff --git a/DigitalAudioH533.ioc b/DigitalAudioH533.ioc index 1b1f8db..9b06398 100644 --- a/DigitalAudioH533.ioc +++ b/DigitalAudioH533.ioc @@ -7,6 +7,20 @@ CAD.pinconfig=Dual CAD.provider=Component Search Engine CORTEX_M33_NS.userName=CORTEX_M33 File.Version=6 +GPDMA1.CIRCULARMODE_GPDMACH1=ENABLE +GPDMA1.DESTINC_GPDMACH1=DMA_DINC_INCREMENTED +GPDMA1.DIRECTION_GPDMACH0=DMA_MEMORY_TO_PERIPH +GPDMA1.IPHANDLE_GPDMACH0-SIMPLEREQUEST_GPDMACH0=__NULL +GPDMA1.IPHANDLE_GPDMACH1-SIMPLEREQUEST_GPDMACH1=__NULL +GPDMA1.IPParameters=IPHANDLE_GPDMACH0-SIMPLEREQUEST_GPDMACH0,REQUEST_GPDMACH0,CIRCULARMODE_GPDMACH1,LINKALLOCATEDPORT_CIRCULAR_GPDMACH1,IPHANDLE_GPDMACH1-SIMPLEREQUEST_GPDMACH1,REQUEST_GPDMACH1,TRANSFERALLOCATEDPORTDEST_GPDMACH1,TRANSFEREVENTMODE_LL_CIRCULAR_GPDMACH1,DIRECTION_GPDMACH0,SRCINC_GPDMACH0,DESTINC_GPDMACH1,TRANSFERALLOCATEDPORTSRC_GPDMACH1,TRANSFERALLOCATEDPORTSRC_GPDMACH0 +GPDMA1.LINKALLOCATEDPORT_CIRCULAR_GPDMACH1=DMA_LINK_ALLOCATED_PORT1 +GPDMA1.REQUEST_GPDMACH0=GPDMA1_REQUEST_USART3_TX +GPDMA1.REQUEST_GPDMACH1=GPDMA1_REQUEST_USART3_RX +GPDMA1.SRCINC_GPDMACH0=DMA_SINC_INCREMENTED +GPDMA1.TRANSFERALLOCATEDPORTDEST_GPDMACH1=DMA_DEST_ALLOCATED_PORT1 +GPDMA1.TRANSFERALLOCATEDPORTSRC_GPDMACH0=DMA_SRC_ALLOCATED_PORT1 +GPDMA1.TRANSFERALLOCATEDPORTSRC_GPDMACH1=DMA_SRC_ALLOCATED_PORT0 +GPDMA1.TRANSFEREVENTMODE_LL_CIRCULAR_GPDMACH1=DMA_TCEM_BLOCK_TRANSFER GPIO.groupedBy=Group By Peripherals KeepUserPlacement=false MMTAppReg1.MEMORYMAP.AP=RW_priv_only @@ -46,18 +60,19 @@ Mcu.ContextProject=TrustZoneDisabled Mcu.Family=STM32H5 Mcu.IP0=BOOTPATH Mcu.IP1=CORTEX_M33_NS -Mcu.IP10=TIM5 -Mcu.IP11=UART5 -Mcu.IP12=USART3 +Mcu.IP10=TIM2 +Mcu.IP11=TIM5 +Mcu.IP12=UART5 +Mcu.IP13=USART3 Mcu.IP2=DEBUG -Mcu.IP3=ICACHE -Mcu.IP4=MEMORYMAP -Mcu.IP5=NVIC -Mcu.IP6=PWR -Mcu.IP7=RCC -Mcu.IP8=SYS -Mcu.IP9=TIM2 -Mcu.IPNb=13 +Mcu.IP3=GPDMA1 +Mcu.IP4=ICACHE +Mcu.IP5=MEMORYMAP +Mcu.IP6=NVIC +Mcu.IP7=PWR +Mcu.IP8=RCC +Mcu.IP9=SYS +Mcu.IPNb=14 Mcu.Name=STM32H533RETx Mcu.Package=LQFP64 Mcu.Pin0=PC14-OSC32_IN(OSC32_IN) @@ -66,15 +81,17 @@ Mcu.Pin10=PC12 Mcu.Pin11=PD2 Mcu.Pin12=PB8 Mcu.Pin13=VP_CORTEX_M33_NS_VS_Hclk -Mcu.Pin14=VP_ICACHE_VS_ICACHE -Mcu.Pin15=VP_PWR_VS_SECSignals -Mcu.Pin16=VP_PWR_VS_LPOM -Mcu.Pin17=VP_SYS_VS_Systick -Mcu.Pin18=VP_TIM2_VS_ClockSourceINT -Mcu.Pin19=VP_TIM5_VS_ClockSourceINT +Mcu.Pin14=VP_GPDMA1_VS_GPDMACH0 +Mcu.Pin15=VP_GPDMA1_VS_GPDMACH1 +Mcu.Pin16=VP_ICACHE_VS_ICACHE +Mcu.Pin17=VP_PWR_VS_SECSignals +Mcu.Pin18=VP_PWR_VS_LPOM +Mcu.Pin19=VP_SYS_VS_Systick Mcu.Pin2=PH0-OSC_IN(PH0) -Mcu.Pin20=VP_BOOTPATH_VS_BOOTPATH -Mcu.Pin21=VP_MEMORYMAP_VS_MEMORYMAP +Mcu.Pin20=VP_TIM2_VS_ClockSourceINT +Mcu.Pin21=VP_TIM5_VS_ClockSourceINT +Mcu.Pin22=VP_BOOTPATH_VS_BOOTPATH +Mcu.Pin23=VP_MEMORYMAP_VS_MEMORYMAP Mcu.Pin3=PH1-OSC_OUT(PH1) Mcu.Pin4=PB1 Mcu.Pin5=PB10 @@ -82,7 +99,7 @@ Mcu.Pin6=PB14 Mcu.Pin7=PA13(JTMS/SWDIO) Mcu.Pin8=PA14(JTCK/SWCLK) Mcu.Pin9=PC11 -Mcu.PinsNb=22 +Mcu.PinsNb=24 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32H533RETx @@ -91,6 +108,8 @@ MxDb.Version=DB.6.0.160 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.ForceEnableDMAVector=true +NVIC.GPDMA1_Channel0_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false +NVIC.GPDMA1_Channel1_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false @@ -186,7 +205,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-LL-false,2-MX_GPIO_Init-GPIO-false-LL-true,3-MX_ICACHE_Init-ICACHE-false-LL-true,4-MX_TIM5_Init-TIM5-false-LL-true,5-MX_TIM2_Init-TIM2-false-LL-true,6-MX_UART5_Init-UART5-false-LL-true,7-MX_USART3_UART_Init-USART3-false-LL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-LL-true,0-MX_PWR_Init-PWR-false-LL-true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-LL-false,2-MX_GPIO_Init-GPIO-false-LL-true,3-MX_GPDMA1_Init-GPDMA1-false-LL-true,4-MX_ICACHE_Init-ICACHE-false-LL-true,5-MX_TIM5_Init-TIM5-false-LL-true,6-MX_TIM2_Init-TIM2-false-LL-true,7-MX_USART3_UART_Init-USART3-false-LL-true,8-MX_UART5_Init-UART5-false-LL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-LL-true,0-MX_PWR_Init-PWR-false-LL-true RCC.ADCFreq_Value=80000000 RCC.AHBFreq_Value=80000000 RCC.APB1Freq_Value=80000000 @@ -277,6 +296,10 @@ VP_BOOTPATH_VS_BOOTPATH.Mode=BP_Activate VP_BOOTPATH_VS_BOOTPATH.Signal=BOOTPATH_VS_BOOTPATH VP_CORTEX_M33_NS_VS_Hclk.Mode=Hclk_Mode VP_CORTEX_M33_NS_VS_Hclk.Signal=CORTEX_M33_NS_VS_Hclk +VP_GPDMA1_VS_GPDMACH0.Mode=SIMPLEREQUEST_GPDMACH0 +VP_GPDMA1_VS_GPDMACH0.Signal=GPDMA1_VS_GPDMACH0 +VP_GPDMA1_VS_GPDMACH1.Mode=SIMPLEREQUEST_GPDMACH1 +VP_GPDMA1_VS_GPDMACH1.Signal=GPDMA1_VS_GPDMACH1 VP_ICACHE_VS_ICACHE.Mode=DefaultMode VP_ICACHE_VS_ICACHE.Signal=ICACHE_VS_ICACHE VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg